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Electrical Test and Fault Tolerance (ETFT)
An Industry-Academia Consortium

Leaders: Professors Abhijit Chatterjee (lead) and David Keezer (ECE)

Goal: Built-in Diagnosis and Test for SIP and SOP

Launch Date: November 2006

Contact: Prof. Abhijit Chatterjee, abhijit.chatterjee@ece.gatech.edu

Focus: This workshop will address the challenges associated with electrical testing for System-In-Package/System-On-Package (SIP/SOP). While considerable improvements have been made in developing test methodologies for high-speed digital ICs, RF ICs and other logic ICs, new test strategies should be developed and applied for 2D and 3D SIP/SOPs. The workshop is intended to address application of Design For Test (DFT) technologies to SIP/SOP modules.

The PRC has developed innovative DFT techniques for digital and RF module and at-speed test technology for Multi-gHz Test of digital ICs.

Proposed Projects

• Low cost 10+ Gbps data transceiver test
• Layout based techniques for correcting systematic process variability effects
• Self-test/self-diagnosis/self-calibration of mixed-technology integrated SiPs
• Combine design and test, test of sensors, monitors and self-calibrating systems, test and fault-tolerance of nanometer devices
• Native mode self-test microprocessor/analog/RF subsystems
• Post silicon debug/diagnosis
• Testing & probing of partial circuits in 3D integration
• Focus effort to yield product solutions for analog BiT

Participating Companies

• Interested companies please contact Prof. Chatterjee, abhijit.chatterjee@ece.gatech.edu