Campus Directory Campus Map College of Engineering Georgia Tech
Georgia Tech >> College of Engineering >> ECE >> PRC
Welcome   |   Academics   |   Students   |   Faculty & Staff   |   Research   |   Industry Partnerships   |  News Archive

Next-Generation Flip Chip: Substrate, Warpage, Interconnects and Assembly (NGFC)
An Industry-Academia Consortium

 

Leaders: Profs. Rao Tummala, GT ECE & MSE (lead) and Suresh Sitaraman

Program Manager: Dr. Nitesh Kumbhat, Georgia Institute of Technology

Launch Date: Fall 2008 | Next Meeting Info & Online Registration

Contact: Dr. Nitesh Kumbhat, nitesh@gatech.edu

Focus: Dramatic growth and advances in semiconductor technology have placed stringent requirements on flip-chip interconnects, substrate wiring, and via density. To achieve high reliability, high wiring and via density, and good assembly yield, there is a need to investigate novel interconnect methods, underfill materials, and cored and coreless substrate materials. In addition, substrate planarity and warpage must be tightly controlled to achieve dimensional stability which becomes even more critical as flexible core-less substrates gain momentum due to cost considerations. The Microsystems Packaging Research Center at Georgia Institute of Technology (PRC-GT) proposes to create an Industry-Academia collaborative consortium to address the interconnects substrate warpage, and assembly challenges in terms of materials, processes and design considerations. The PRC-GT is working on several innovative approaches that include novel interconnects, new underfills, substrate and dielectric materials and their processing, warpage prediction models, ECAD-MCAD integration tools, as well as guidelines for warpage reduction.

Proposed Projects

1. Novel Interconnects and Underfill
   • Advanced UBM for electromigration
   • Nano-composite solders for enhanced reliability
   • Novel low stand-off and fine pitch underfill material and process
2. Organic Substrates
   • Low and medium CTE substrates for fine pitch flip-chip reliability
   • Fine pitch wiring processes for sub-10µm lines/spaces and sub-25µm vias for area array fine pitch flip-chip interconnect
   • Fine-pitch assembly with ultra-thin core and coreless substrates
3. Module and Substrate Warpage: Modeling, Measurement, and Control
   • Design and Simulation
     • ECAD to MCAD – seamless analysis techniques
     • Trace layout and local substrate behavior
     • Core and coreless substrates with build-up layers – warpage prediction
     • Metrology and Validation
   • Warpage measurement metrology
     • Core substrate warpage measurement
     • Coreless substrate warpage – gravitational effects
     • Warpage Reduction and Targets
     • Processing conditions and warpage
     • Material selection and warpage
     • Trace layout and warpage
       

Participating Companies

• To be listed soon