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A major bottleneck in the development of next generation packaging technologies is the design tools. Due to the integration of heterogeneous functions in a package, mixed signal design tools are necessary that are part of a design flow. The Packaging Research Center (PRC) at Georgia Institute of Technology has been one of the pioneers in this area, introducing tools that address the System-on-Package (SOP) technologies. Design of such highly integrated mixed-signal systems require new tools that, for example, take into consideration the increased interaction between the IC and package leading to system miniaturization. This workshop is targeted to discuss the electrical and mechanical issues arising in mixed signal design, leading to the development of mixed-signal design tools through the formation of a consortium of companies at PRC, which can provide solutions in this area.

Topics

• Design Flow
• Electrical Chip-Package Co-Design
• Signal and Power Integrity
• Design Tools for RF Packaging
• Electromagnetic Analysis
• Circuit Analysis Methods
• Design for Manufacturing
• Physical Design

Who Should Join?

Scientists, engineers and managers from, semiconductors, package and electronic systems in automotive, mobile communications, defense and aerospace industries are invited to attend the workshop.

Agenda
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April 16, 2009

8:30am – 9:00am Welcome and Overview – Prof. Madhavan Swaminathan

Session 1: EDA for Digital and Mixed Signal
9:00am – 9:05am Overview – Dr. Daehyun Chung
9:05am – 9:30am MSDT 1: Power Ground Network Simulator and Optimizer
Technical Presentation – Jaeyoung Choi (20 min)
Q&A (5 min)

9:30am – 9:55am MSDT 2: Design for Manufacturing Methods for SiP
Technical Presentation – Dr. Sunghwan Min (20 min)
Q&A (5 min)

9:55am – 10:10am Break

10:10am – 10:35am MSDT 5: EBG Modeling and Synthesis
Technical Presentation – Bernie Jord Yang (20 min)
Q&A (5 min)
10:35am – 11:30am Demo (MSDT 1,2)

11:30am – 11:45am Break

11:45am – 12:15pm Demo (MSDT5)

Session 2: EDA for RF
12:15pm – 12:20am Overview – Dr. Sunghwan Min
12:20am – 1:10pm MSDT 3: Automated methods for the design of EP
3.1: Technical Presentation – Narayanan T V (20 min)
Q&A (5 min)
3.2: Technical Presentation – Mohit Pathak and Prof. SungKyu Lim (20 min)
Q&A (5 min)
1:10am – 1:40pm Demo (MSDT3.1)

April 17th

8:00am – 8:25am MSDT 7: Parametric models of Linear 3D Electrical Interconnects and Packages (EIP)
Technical Presentation – Prof. Stefano Grivet, U. of Torino (20 min)
Q&A (5 min)

Session 3: EDA for 3D Multiscale Integration
8:25am – 8:30am Overview – Prof. Madhavan Swaminathan
8:30am – 8:55am MSDT 4: EM Simulator for Chip-Package Co-Design
Technical Presentation – Myunghyun Ha (20 min)
Q&A (5 min)
8:55am – 9:20am MSDT 6: Modeling of Coupling in 3D Integration
Technical Presentation – KiJin Han (20 min)
Q&A (5 min)

9:20am – 9:35am Break

Session 4: IAB Feedback - Chairs: Dr. Jochen Reisinger (Infineon) and Dr. Karl Wagner (Epcos)
9:35am – 10:15am Closed door IAB (Panasonic, Sameer, Epcos, Infineon, NXP)
10:15pm – 11:15am Industry Feedback

11:15am – 11:30am Break

11:30am – 12:00pm Demo (MSDT 3.2)
12:00pm – 12:30pm Demo (MSDT7)
12:30am – 1:00pm Demo (MSDT4)
1:00pm – 1:30pm Demo (MSDT6)
1:30pm – 2:00pm Wrap – Up