PRC INDUSTRY WEEK & CONSORTIA DEVELOPMENT
RESEARCH INNOVATIONS
PATENTS & INVENTIONS
CONFERENCES & WORKSHOPS
MEMBERSHIPS & CONTRACTS
PUBLICATIONS

PRC STUDENT HIGHLIGHT
PRC INTERNATIONAL PICNIC
STUDENTS' CORNER
AWARDS & RECOGNITION
FACULTY
PRC JOB OPPORTUNITIES

PRC INDUSTRY WEEK & CONSORTIA DEVELOPMENT - September 17-21, 2007

IAB Meeting for PRC Project Member Companies, September 17, 2007
On Monday, September 17th, 2007, an IAB meeting for PRC project member companies will be held at GT-PRC. The IAB event will begin with one-on-one meetings where individual research projects will be discussed with PRC faculty and staff, followed by sessions of alliance research projects review, PRC seed funded research review, and membership and IP management. For further information, please contact cyoon@ece.gatech.edu or visit www.prc.gatech.edu/events/iab.

IAB Meetings for EMAP Program Member Companies, September 18, 2007
GT-PRC launched the Embedded Actives and Passives (EMAP) consortia program on January 8th, 2007. The second meeting for this consortium will be held on Tuesday, September 18th, 2007. PRC consortia meetings are designed to review research projects, encourage industry feedback and manage IP issues. In addition to these activities, student posters and demonstrations of research outcomes are also included in the day-long meetings. For further information, please contact vsunda@ece.gatech.edu, or visit www.prc.gatech.edu/events/emap.

Industry Forum Day, September 19, 2007
Georgia Tech Packaging Research Center (PRC) announces its second Industry Forum Day on Wednesday, Sept. 19th, 2007, to be held at the Georgia Tech campus. The Industry Forum Day will feature keynotes from industry visionaries from major global players in semiconductor, consumer electronics, avionics, bioelectronics, and Georgia Tech research leaders in IC design, NEMS and sensors, nanotechnology and system integration by SOP technology. Furthermore, the Industry Forum also will provide a session specially designed to enhance interaction between companies and students, through student posters, company-student one-on-one, industry presentations and table-top exhibits. For further information, please contact cyoon@ece.gatech.edu or visit www.prc.gatech.edu/events/indforum07.

IAB Meeting for TIM Program Member Companies, September 21, 2007
The TIM consortium workshop will hold its next meeting for TIM member companies on September 21, 2007 at the Georgia Tech Packaging Research Center. The meeting will be held at the Manufacturing Research Center auditorium beginning at 9am and will be chaired by Prof. Yogendra Joshi. The day’s activities will include TIM Project Review on topics such as TIM materials and interfaces, assembly and bonding, characterization, reliability, followed by the Consortia Program Management Plan headed by Dr. Chong Yoon and will end with a Member Feedback and Discussion session. For further information, please contact Dr. Chong Yoon at cyoon@ece.gatech.edu or visit www.prc.gatech.edu/events/tim

3D Silicon SOP Consortium Workshop
The 3D Silicon SOP (3DSiSOP) consortium workshop has been postponed until February 2008. Please visit the PRC website for updates on the development of this program. www.prc.gatech.edu

Industry-PRC Consortia Development:
www.prc.gatech.edu/consortia

IAB Meeting for MSDT Program Member Companies, November 1, 2007
GT-PRC consortia program, Mixed Signal Design Tools (MSDT), was launched on January 8th, 2007. There have been six paper submissions to conferences and one invention disclosure supported by MSDT since its launch. The second IAB meeting for MSDT will be held on November 1st (Thu), 2007 at GT-PRC. The IAB meeting is designed for review of research projects, industry feedback and IP management. In addition to this, student posters and demonstrations of the tools are also included in the day-long meeting. For further information, please contact engin@ece.gatech.edu, or go to www.prc.gatech.edu/events/msdt.

IMEC and Georgia Tech Offer Joint Program to Solve Packaging Interconnect Gap

The Packaging Research Center at Georgia Tech (GT-PRC)-Atlanta and IMEC invite interested parties from global industry to join their advanced research program on next-generation flip chip and substrate technology. The program addresses the key ‘IC-to-package to board’ packaging interconnect issues for 32nm ICs and beyond.

Building on their complementary capabilities, IMEC and Georgia Tech have joined forces by setting up an industrial affiliation program to solve the packaging interconnect gap. Together with their industrial parties, they will explore, develop and invent new solutions to interconnect high-density ICs with very tight I/O pitches (down to 40-20µm peripheral) to low-cost packages and printed circuit boards. The program targets novel packaging approaches to reduce the mechanical stress on the IC with its ultra low k dielectrics after packaging and assembly. These low-stress packaging techniques become indispensable when using Cu/low-k on-chip interconnections, since low-k materials typically have very weak mechanical properties.

The program will provide solutions for the four major barriers to next-generation flip-chip packaging of scaled ICs and ultra-low-k dielectric ICs. Aim is to explore and develop:

1. Organic package interposer substrates that minimize stress at die and package level and  enhance the wiring density, the fine I/O pitch routing capability and the high-frequency signal performance of  substrates;
2. A new generation of fine-pitch flip-chip UBM (under-bump metallization) and barrier metallization that meet the electro-migration and thermo-mechanical reliability targets of flip chip scaling;
3. Novel solder and non-solder interconnect approaches including advanced underfill materials and processes to meet future current density, geometry and reliability requirements;
4. Thermo-mechanical modeling, design and verification for improved reliability.

The 2-year program is open for the entire supply chain including system companies, IC manufacturers and assembly houses. Partners can benefit from the complimentary expertise of Georgia Tech, a global leader and pioneer in package and system integration, and IMEC, a pioneer of silicon-centric technologies. The extensive state-of-the-art facilities for packaging and semiconductor processing, fabrication and integration at both institutes are major assets of this program.

“We are excited to start this unique open program with Georgia Tech where we intend to bring together 20-30 expert researchers from industry and academia worldwide;” said Eric Beyne, Scientific Director Interconnect, Packaging and Systems Integration at IMEC. “Only by joining expertise and know-how from leading players in the packaging and semiconductor field, we will be able to realize highly reliable solutions beyond the traditional flip chip interconnections.”

The Georgia Tech–IMEC synergy in expertise and facilities in ICs packages and systems is critical to address the barriers in flipchip reliability, electro-migration, ultra fine pitch I/O substrates and IC-package interconnections. “I believe the IMEC-Georgia Tech team can help the global industry in an unparalleled way,” said Prof. Rao Tummala, Professor and Director of the Packaging Research Center. Please contact Pulugurtha Markondeya Raj (raj@ece.gatech.edu) for more details.

Embedded Module with Active and Passive Components (EMAP) Consortium Focusing on Next Generation Mixed Signal Modules/Packages for Wireless and Mobile Product Applications

Excellent progress in key research themes in the first two quarters

The focus of the EMAP consortium is the development of next generation mixed signal modules with embedded active and passive components to further miniaturize current SiP (System in Package) and SoP (System on Package) technologies. The major emphasis of the EMAP consortium is on mobile product applications with focus on RF/wireless modules/packaging, and baseband processor packaging for cellular, WLAN, WiMAX and other wireless communication systems.

The Industrial Advisory Board (IAB) for the EMAP consortium consists of Bosch (Germany), Draper Labs (USA), Epcos (Germany), Infineon (Germany), Sameer (India), and Texas Instruments (USA). We would like to welcome our newest member to the IAB, Intel Corporation (USA) who joined the program recently. The consortium research is supported by a group of supply chain partners including AT&S (Austria), Disco (Japan/Singapore), DuPont Electronic Materials (USA), Endicott Interconnect (USA), Ibiden (USA/Japan), Oak-Mitsui Technologies (USA/Japan), Rogers Corporation (USA), Starfire Systems (USA).

The consortium research program with ten research projects was kicked off in March 2007 for Phase 1 duration of two years. The major technology themes that are being addressed include:

• EMAP Design and Characterization
• Ultra Thin Substrate, including thin core, thin low loss build-up dielectrics and embedding active ICs in substrate cavities with a chip-last approach
• Ultra Thin Silicon Die, including wafer thinning and dicing, handling, characterization and drop impact studies
• Chip-Last Die-to-Package Interconnection including Cu Bump bonding methods and self-assembly processes
• Thermal Management via advanced passive cooling technologies
• Embedded RF MEMS Switch

For the first two quarters of the program, good progress has been reported in all the research projects and several demonstrations are planned for the end of the first year.

Companies interested in joining the consortia are encouraged to contact Venky Sundaram (EMAP Program Manager, vsunda@ece.gatech.edu), Dr. Mahadevan Iyer (Research Director, mahadevan.iyer@ece.gatech.edu), or Prof. Rao Tummala (PRC Director, rao.tummala@ece.gatech.edu).

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The following article featured the PRC's first Industry Forum Day in March 2007. Used with permission Jennifer Greene, Staff Writer, Georgia Tech School of ECE.

PRC Presents Its First Industry Forum Day in March 2007
Jennifer Greene, Staff Writer, Georgia Tech School of ECE

Georgia Tech’s Packaging Research Center (PRC) held its first Annual Industry Forum Day in Micro, Nano, and Bio Electronics on March 14. Attendees included technical leaders and managers from academia and industry. Sixty companies, 20 Tech faculty members, and 50 Tech graduate students participated in the event, which was held at the Manufacturing Research Center.

“It was an exciting day for Georgia Tech and for global industry,” said Rao R. Tummala, PRC director, Joseph M. Pettit Chair in Electronics Packaging, and Georgia Research Alliance Eminent Scholar. “Industry visionaries shared their thoughts about ICs, avionics, bioelectronics, and consumer electronics, and we shared what we are doing at Georgia Tech in the same areas. I expect this kind of forum to lead to more collaborative research programs between Georgia Tech and global industry.”

Industry Forum Day featured keynote presentations by industry executives from Advanced Bionics, Rockwell Collins, Sony Corporation, and Texas Instruments. The talks focused on future technology directions in integrated circuits, packaging, and systems for consumers, computers, mobile communications, aviation electronics, and bioelectronics.

Several Georgia Tech representatives presented the Institute’s latest advances in micro, nano, and bio systems research.  Research engineer Azad Naeemi shared the work that he and James D. Meindl, director of the Microelectronics Research Center, are doing on interconnects for nanoelectronics. Dr. Tummala discussed PRC's vision of system-on-package as potentially the Second Law of Electronics for system integration. Madhavan Swaminathan, Joseph M. Pettit Professor in Electronics and PRC deputy director, spoke about mixed-signal system design. Mark Allen, Joseph M. Pettit Professor and co-founder of CardioMEMS, concluded this segment of the program with an overview of nanoelectromechanical systems (NEMS) and sensors.

Following these remarks, a career fair was held in the atrium. The fair included student posters, supply chain company presentations, and student recruiting meetings.

Industry Forum Day was part of PRC’s 2007 Industry Week, which took place March 13-16. Other highlights of the week included NanoPack--a nano packaging, components, and systems event--and several Industrial Advisory Board meetings on PRC projects.

The next Industry Forum will be September 17-21, 2007. See www.prc.gatech.edu/events/glance for further information.

RESEARCH INNOVATIONS

PRC Develops Novel Maskless Micropatterning of Nanometallic Structures
PRC is focusing on thin film bonding and fine pitch interconnection for Si-SOP and next-generation flip chip on organic substrates. Recently, PRC students Gopal Jha and Gaurav Mehrotra demonstrated a novel maskless micropatterning of high conductivity nanoparticles and nanogels. Such technique can enable single step patterning-synthesis and bonding of nanointerconnection materials and thus reduce the cost, complexity and time of production. The process involves selective wetting of metal bond pad with nanoparticles or solution derived gels, followed by reduction and bonding with the metallic nanostructures. This method is helpful in bonding copper-copper interconnection at very low temperature and pressure. Notably, it also presents better alternatives without issues such as intermetallics and electromigration. Nanogranular copper offers quantum jump in electrical performance over the conventional interconnections based on lead/lead free solders. It is a non-collapsible thin film interconnection and can result in ultrafine pitches. Please contact Pulugurtha Markondeya Raj (raj@ece.gatech.edu) for more details.

A Non-destructive and Real Time Characterization Technique for Low Loss Optical Polymeric Waveguide and Lightwave Circuits
Optical polymer waveguide is a key passive component for the optical interconnection. Design, fabrication, and characterization of high performance waveguides have a critical importance for the success of optoelectronic integration. We have developed a fast, non-destructive, sensitive, and real-time technique for detailed investigation of the propagation properties of planar optical waveguides. A high sensitive CCD camera with a built-in integration function is utilized to observe the light streak in two dimensions through a two lens imaging system. A few seconds to a few ten seconds (depending on the beam scattering intensity) is needed to complete one measurement, compared to the sliding prism method requiring several hours and cutback method requiring even longer time. We used this technique to demonstrate high performance polymer waveguides on PCB substrates with propagation loss less than 0.05dB/cm. To the best of our knowledge, this is in the lowest loss data reported for polymer waveguides on PCB substrates to date. This technique can not only be used to evaluate the overall performance of a waveguide but also localized waveguide performance. In addition, it can be used for processing quality monitor and assembly alignment control for the electronic-optical integration and extended to in-situ investigation of the propagation properties such as defect effect, mode profile, bending properties, coupling and cross talking etc. in the lightwave circuit.
In summary, the advantages of the technique are:

• Ideal for the complex waveguide circuits and geometries, local and overall
• Real time measurement
• Fast
• Non-destructive technique
• Independent of the coupling efficiency
• No scanning mechanisms involved
• Lightwave circuit monitoring

It is believed that this technique can be a powerful tool for studying the performance, process control and monitoring the optical interconnection and lightwave circuits. Please contact Dr. Fuhan Liu (fliu@ece.gatech.edu) for more details.

Conformal and Miniaturized Antennas on Flexible, High-K and Nanomagnetic Substrates for WLAN and WiMaX Applications
Conformal antennas on flexible substrates and miniaturized antennas on nanomagnetic materials are being investigated at PRC. By using the novel fabrication techniques developed at PRC, conformal antennas on 1 mil thick, very flexible Liquid Crystalline Polymer (LCP) based substrates have been fabricated. The fabricated designs were measured and good correlation between measurement and simulation results were observed. The next step in this research is the integration of other front-end components, such as filters, to the antenna. The usage of magnetodielectric materials in antenna miniaturization is also being investigated. Magnetodielectrics, unlike high-k materials, provide both wide bandwidth and high efficiency while miniaturizing the antenna. PRC researchers are currently developing engineered materials that can provide both magnetic and dielectric properties for the microwave region operation to be employed for miniaturized antenna design. Contact: Dr. Ege Engin (engin@ece.gatech.edu).

PRC First to Fabricate and Develop Integrated Planar Miniaturized Electrochemical System with New Sensing Concepts
The PRC is the first to fabricate and develop integrated planar miniaturized electrochemical system with new sensing concepts such as zirconia-nafion encapsulants and embedded carbon nanotubes (CNTs) for high enzyme stability and sensitivity. Pt, silver and glassy carbon electrodes are integrated at low temperatures to enable organic compatible processes. The sensitivity to glucose detection at 5 millimolar concentrations is demonstrated using glucose oxidase enzyme.The miniaturized electrochemical system is suitable for on site and real-time detection and measurements of oxidative stress biomarkers present in least quantities such as nitric oxide (NO), hydrogen peroxide (H₂O₂) superoxide dismutase (SOD), 8-isoprostane and NAD (H) P oxidase enzyme activity in the cardiovascular and brain diseases. Microfluidic channels with cross sectional dimensions in the order of 10-100 μm. are fabricated and integrated with the multiplexed nanobio sensors system. A low cost polydimethylsiloxane (PDMS) adhesive based bonding is used to seal the channels. These channels guide and help biofluids carrying the target or the sample to be tested onto sensing elements of the bio-sensor, particularly in multiplexed system for detection of several different target molecules simultaneously.

The detection and quantification of biological and chemical species in least quantities is central to early detection of diseases, food contamination and environmental security. Detection of the most common biological molecular interactions such as antigen/antibody interactions, nucleic acid interactions, enzymatic interactions, cellular interactions, and biomemetic or synthetic molecular interactions by electrical methods is gaining prominence in terms of sensitivity and rapidity. The electrical biosensors measure the change in conductance/resistance (impedance), current density (amperometric), oxidation /reduction of potential of an electrochemical reaction or capacitance in biological molecular interactions. The change is measured and calibrated to a proper scale.

The Packaging Research Center (PRC) at Georgia Tech is focused on development of conductimetric and electrochemical sensors. The conductimetric biosensors are fabricated using ZnO nanowire and ZnO thin films, and demonstrated the real-time detection of protein and cellular recognition and hybridization. The fundamental sensing mechanism of the metal oxide based sensors relies on a change in electrical conductivity due to the interaction process between the surface complexes such as O-, O2-, H+ and OH- reactive chemical species. The applications of this detection system include early detection of breast cancer, food and drink pathogens such as E.coli and Salmonella. The sensitivity thresholds are in the range of sub-picogram.

Please contact Drs. Janagama Goud (jgoud@ece.gatech.edu) or Pulugurtha Markondeya Raj (raj@ece.gatech.edu) for more details.

PRC SOP Substrate Research Team Pushes Organic Substrate Technology to New Dimensions
Research on next generation of organic substrates for SOP, SiP and high density flip-chip packaging is focused on enhancing all major processes associated with ultra-fine line copper conductors and multilayer stacked microvias. In partnership with global supply chain companies, several low and medium-CTE core materials have been integrated into multilayer build-up substrate test vehicles. The target copper line width and space on build-up layers is 3-10µm using organic package substrate concepts such as thin dry film and low cost liquid resist lithography, electroless and electrolytic semi-additive plating. Another key theme is the adhesion of polymer to copper for multilayer bond strength enhancement with progressively lower interface roughness for high frequency and high speed applications. Recent research in collaboration with Atotech, (Berline, Germany) on novel chemical bonding based copper surface treatment technology has demonstrated the capability to achieve good peel strength while maintaining the "as-plated" integrity of sub-10µm copper conductors. The SEM micrograph shows excellent line width control of 10µm lines and spaces (8-10µm Cu thickness) after SecureTM HFz (Atotech) copper treatment process on Ajinomoto Build-up Film (ABF) dielectric with permanganate desmear treatment and average roughness (Ra) of around 1µm. This research was presented at the recent ECTC conference in Reno, NV in June 2007. For more information, please contact Venky Sundaram (vsunda@ece.gatech.edu) or Prof. Rao Tummala (rao.tummala@ece.gatech.edu). For additional information on Atotech technology, please contact Hugh Roberts (hugh.roberts@atotech.com)

Novel Low Loss Ultra-Thin Film Dielectrics for Next Generation RF and Digital Package Substrates
In the past ten years, the PRC team has been exploring the integration of new thin film dielectric materials and processes for next generation SOP and high frequency package substrates. New processes compatible with package substrate infrastructure have been demonstrated for liquid spin-on low-loss thin films including BCB, and dry films including liquid crystal polymer (LCP), A-PPE and advanced epoxy dielectrics. The current research includes on a new generation of thin film build-up dielectric from Rogers Corporation. This thermosetting resin system has excellent high frequency performance into the multiple GHz range due to stable and low loss tangent (<0.005) and low dielectric constant (2.5-3.5). Ultra-thin films down to 6µm thickness on plastic carriers or very low profile copper foil (RCF) have been integrated on thin core glass-reinforced laminates having similar properties. A second resin system has also been investigated for it low stress properties for high density flip chip package substrates. Thin dry films of 10µm and 25µm thickness have been fabricated on BT laminate cores and these films are expected to provide superior resistance to cracking when used on thinner cores that will be necessary for future sub-100µm pitch flip chip substrates. Both these dry film materials exhibit excellent planarization as illustrated in the adjoining figure. Research on ultra-small microvias (<25µm) and ultra-fine line metallization using these novel dielectrics is on-going. For more information, contact Dr. Fuhan Liu (fliu@ece.gatech.edu) or Venky Sundaram (vsunda@ece.gatech.edu). For more information on the Rogers materials, please contact Dirk Baars (dirk.baars@rogerscorporation.com, Scott Kennedy (scott.kennedy@rogerscorporation.com) or John Dobrick (john.dobrick@rogerscorporation.com).

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PATENTS & INVENTIONS

“Electromagnetic Bandgap (EBG) Structure for Isolation in Mixed-signal Systems” - Innovators: Jinwoo Choi, Madhavan Swaminathan, Vinu Govind - Submitted Sep. 08, 2004 - An embodiment of the EBG structure, among others, is configured to substantially filter electromagnetic waves to a stopband floor of ~-40 dB to ~-120 dB in a bandgap of ~100 MHz to ~50 GHz having a width selected from about 1, 2, 3, 5, 10, 20, and 30 GHz, with a center frequency from ~1-37 GHz.

“Trench-Enabled Simultaneous Alignment Technique for Optical Device Integration” - Innovator: Daniel Guidotti - Submitted March 3, 2007 - Enables simple, manufacturable, inexpensive, and fast processes that are compatible with standard CMOS processing and could be easily implemented using current flip-chip bonding techniques and standard photolithography instrumentations.

“Bumpless, No-Reflow Interconnect and Assembly Process for Ultra-Fine Pitch Flip-Chip” - Innovator: Fuhan Liu - Submitted June 8, 2007 - Metal-to-metal direct thermosonic bonding using metal studs on substrate to develop a novel chip-to-package interconnection based on bumpless, no-reflow chip bonding to substrate.

“Biosensor Integration Methods with Advanced Working Electrodes and Enzyme Encapsulation Techniques” - Innovator: Goud Janagama - Submitted June 14, 2007 - Electrochemical detection of the smallest quantities of proteins, peptides, DNA, RNA, glucose and enzyme kinetics by integrating carbon electrodes increasing sensitivity and reliability of detection system.

“Novel Nanoscale Ferroelectrics and Ferromagnetics for Noise Isolation in IC's, Packaging and System Architectures” - Innovator: Raj Pulugurtha - Submitted June 19, 2007 - Isolates noise coupling with smaller than film structures and tunes the isolation frequency.

“Compatible Thin Film Resistor and Capacitor Integration on the Same Layer” - Innovator: Raj Pulugurtha - Submitted June 19, 2007 - Currently, there is no solution for low cost embedded capacitor and resistor technology. Manufacturers depend on bulky surface mount components that limit system performance and miniaturization. True system integration and miniaturization is only possible with the thin film embedded capacitor and resistor components described in this invention.

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NEW MEMBERSHIPS, PARTNERSHIPS & CONTRACTS

The PRC’s growth over the past year has been remarkable. Members currently consist of 36 companies and organizations. The PRC’s membership and partnership programs include: Full Projects, Consortia Development, Supply Chain, and Subcontractor. To learn how your organization can access the PRC’s research resources, we encourage you to visit our website at www.prc.gatech.edu/memberinfo.

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PUBLICATIONS

Papers Published at 57th ECTC (Reno, Nevada)

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PRC STUDENT HIGHLIGHT

Nithya Sankaran: Experience at PRC and Internship with Texas Instruments

I have been working with the Packaging Research Center as a Graduate Research Assistant under the advice of Prof. Rao Tummala since fall 2005. My research is focused in the design, modeling, fabrication, and testing of ultra thin packages with embedded active chips using an innovative chip last approach. Currently, I am developing electro magnetic models to study the various transitions and performing design optimization for efficient signal transmissions in an embedded chip environment. This research work is a part of Embedded Actives and Passives (EMAP) research industry consortium initiated by PRC early this year.

Currently I am doing an internship with Texas Instruments. This, being my first internship in graduate studies, has given a very good opportunity to understand how a semiconductor industry functions and the various work areas involved. One develops an idea as to what will suit them the best when looking for a job. Texas Instruments has a very organized co-op program, in which students are provided with a friendly atmosphere and are well guided through their assigned tasks. 

I have very much enjoyed working with PRC. It creates a very good opportunity for students to gain knowledge on electronic packaging and provides them with a lot of infrastructure facilities for practical training. I joined in 2005 as a Masters student, but within a semester I decided to go for a PhD. Students have opportunities to attend and present their research findings in leading conferences and are very well supported and guided by the PRC research team. I attended the ECTC 2007 conference in Reno last month to present a paper and had a very good experience. Through the various industry funded research programs at PRC, we also get to interact closely with industry people, understand materials, IC and system needs and learn their expectation which helps in preparing as potential candidates for jobs.  PRC is truly a great place providing students an excellent opportunity to excel.

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STUDENTS' CORNER

IEEE/CPMT Student Chapter hosts booth at 57th ECTC in Reno, Nevada
By Grace Li, IEEE-CPMT Student Chapter

The IEEE/CPMT Student Chapter of Microsystems Packaging Research Center (PRC) had a booth at the 57th Electronic Components Technology Conference (ECTC) 2007 in Reno, NV. ECTC is a premier international conference jointly sponsored by the IEEE Components, Packaging and Manufacturing Technology Society (CPMT) and the Electronic Components, Assemblies, and Materials Association (ECA), the electronic components sector of the Electronic Industries Alliance (EIA).

The technical program of ECTC contains papers that covers leading edge developments and technical innovations across the packaging spectrum with topics that include advanced packaging, modeling & simulation, optoelectronics, interconnections, materials & processing, quality & reliability, manufacturing technology, Components & RF and Emerging Technologies. At the booth, our chapter members presented our research highlights and activities of our organization for the past year. We also introduced and discussed the System-On-Package (SOP) technology with many industry people.

This booth at ECTC offers a great opportunity for our students to build up more interactions with industry. The chapter members also shared information with a few other IEEE/CPMT student chapters around the world, which will help the development and improvement of our chapter for the next year.

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PRC International Picnic

In June, the PRC held its first International Summer Picnic outside the Manufacturing Research Center building on the Georgia Tech campus. It was a delightful opportunity to enjoy good food from an international selection of cultures and cuisines, play some games and relax at the same time.

The picnic was organized by Patricia Allen, PRC’s new event coordinator, and featured a game designed to help us know more about each other’s interests—outside our career fields. It was a fun afternoon!

Among those attending were a number of visitors from Sony-Japan. Also attending were PRC directors Rao Tummala, Madhavan Swaminathan, Mahadevan Iyer, and Dean Sutter. Researchers, administrative staff, faculty and visiting engineers were also in attendance.

AWARDS & RECOGNITION

Prof. Rao Tummala Receives 2007 IEEE David Feldman Award Rao Tummala, ECE professor, received the 2007 IEEE David Feldman Award, given by the IEEE/CPMT Society. The David Feldman Award, the highest honor given by IEEE/CPMT, recognizes outstanding contributions to the fields encompassed by the Society through executive or managerial directions. Tummala is being recognized for the breadth of his contributions to IEEE/CPMT in numerous leadership roles and their global impact, including his unprecedented two terms as the Society's president.
Madhavan Swaminathan Selected for the SRC GRC Technical Excellence Award ECE chair professor, Gary May, recently congratulated Prof. Madhavan Swaminathan and his students, Rohan Madrekar, Jinwoo Choi, and Krishna Srinivasan, on being chosen for the 2007 Technical Excellence Award given by the Semiconductor Research Corporation and the Global Research Corporation. They are being recognized for their work entitled "Modeling and Co-Simulation of Power Distribution Networks for Digital and Mixed Signal Systems" and will be presented with the award at TECHCON 2007, to be held September 10-12 in Austin, Texas.
ECTC Recognizes Outstanding Poster Paper The 56th Electronic Components and Technology Conference (ECTC) recognized Tae Hong Kim, Ege Engin, Wansuk Yun, Madhavan Swaminathan (GT), Daehyun Chung (KAIST), and Yoshitaka Toyota (Okayama University) for “Outstanding Poster Paper”, entitled, "A Novel Synthesis Method for Designing Electromagnetic Band Bap (EBG) Structures in Packaged Mixed Signal Systems".
Prof. C. P. Wong Receives 2007 Sigma Xi Monie A. Ferst Award Congratulations on being selected as the winner of the 2007 Sigma Xi Monie A. Ferst Award! The Award is given annually to an educator in engineering or science who has made "notable contributions to the motivation and encouragement of research through education." Its purpose is to "recognize significant contributions to scientific research by an educator in engineering or science." It consists of a medal and $5,000 and is made annually to an educator who has inspired his or her colleagues to significant scientific achievements. A one-day Sym. will be held on 9/17 at GT in honoring the Awardee.
ECE Researcher Myung-Jin Yim to Receive Young Engineer Award A Georgia Tech COE researcher was recently picked as the recipient of the Outstanding Young Engineer Award for 2007, given by the IEEE/Components, Packaging and Manufacturing Technology (CPMT) Society. Myung-Jin Yim, a 34-year-old researcher in ECE, won the prestigious award which has been given to a promising young engineer since 1996 on various criteria such as contributions to technology and product development. The award will be presented to Yim at the IEEE/CMPT meeting that will be held in Reno, Nev., May 29-June 1. The IEEE/CPMT Society is the leading international forum for scientists and engineers engaged in the research design and development of advances in micro-systems packaging and manufacturing.
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FACULTY

Professor Yogendra Joshi
John M. McKenney and Warren D. Shiver Distinguished Chair in Building Mechanical Systems and Associate Chair for Graduate Studies

Microelectronics and Emerging Technologies Thermal Laboratory: www.me.gatech.edu/METTL

Yogendra Joshi is Professor and John M. McKenney and Warren D. Shiver Distinguished Chair at the G.W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology.  He directs the Microelectronics and Emerging Technologies Thermal Laboratory (METTL), as well as the Consortium for Energy Efficient Thermal Management (CEETHERM).  During academic years 2003-2007 he also served as the Associate Chair for Graduate Studies for the largest Mechanical Engineering academic program in the country.  Prior to joining the Georgia Institute of Technology in Fall 2001, he held academic positions at the University of Maryland at College Park (1993-2001) and the Naval Postgraduate School (1996-1993).

Dr. Joshi received a Bachelor of Technology degree in Mechanical Engineering from the Indian Institute of Technology in Kanpur in 1979, Master of Science in Mechanical Engineering from the State University of New York, Buffalo in 1981, and a Doctor of Philosophy in Mechanical Engineering and Applied Mechanics, from the University of Pennsylvania in 1984.  He is an elected Fellow of the ASME and the American Association for the Advancement of Science. He has served as Associate Editor for the ASME J. of Electronics Packaging for two terms and is currently an Associate Editor for the J. Heat Transfer.  He was a co-recipient of ASME Curriculum Innovation Award (1999), Inventor Recognition Award from the Semiconductor Research Corporation (2001, 2007), and the ASME Electronic and Photonic Packaging Division Outstanding Contribution Award in Thermal Management (2006).  He serves as the Theme Leader for Thermal Management and Power Delivery for the multi-university Interconnect Focus Center.  He is the author or co-author of over two hundred publications, including over one hundred archival journal articles.  He has advised or co-advised forty seven graduate students, all of whom are well employed.

Dr. Joshi’s research is sponsored by a number of government agencies, and industries. He is leading the Thermal Interface Materials Consortium effort within PRC.  His broad research interests are in the following areas:

• Energy Efficient Thermal Management of Technology Infrastructure Facilities: Computational and experimental studies of data centers.  Facility level implementation of high performance cooling techniques, including liquid cooling.  Air flow modeling within data centers.

• Micro-thermal Systems:  Use of microfabrication techniques to develop compact thermosyphons and heat exchangers.  Modeling of micro-thermal systems.

• Conjugate Transport Mechanisms in Multi-Scale Systems:  Development of experimentally validated modeling methodologies to analyze multi-mode transport in discretely heated systems with multiple length scales spanning over eleven decades.  The application of these to electronics thermal management is targeted.

• Thermal Management of Electronics for Harsh Environments:  Use of phase change energy storage materials for handling harsh environments.  Conjugate modeling for high temperature environments.

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PRC JOB OPPORTUNITIES

The PRC announces job opportunities for anyone qualified for the following positions:

• Assembly & Reliability Test Engineer

• Embedded Components Materials and Process Research Engineer

• Postdoctoral Electrical Design Research Engineer

If you are interested, we encourage you to apply. You can view position details and send us your resume from www.prc.gatech.edu/prcjobs

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